1. Field of the Invention
This invention relates to a circuit for providing redundancy in response to electrical control signals and more particularly to a circuit for substituting spare rows or columns of memory elements in a memory array in place of faulty rows or columns.
2. Description of the Prior Art
Semiconductor memories are being manufactured in the U.S. wherein a memory array of elements is accessed by a row decoder and column decoder to address a particular memory element or row of memory elements in the memory array. A sense amplifier built in a semiconductor chip senses the memory state of the selected memory element when addressed by the row decoder and column decoder. The density of the memory array on a semiconductor chip has increased from 16,000 memory elements to 64,000 memory elements and higher in recent years. As the memory size has increased, the difficulty of building perfect semiconductor memory chips has increased significantly. To improve the situation, redundant memory bits in the form of additional rows or columns in the memory array have been included on the semiconductor chip. The semiconductor memory is first tested while it is in a semiconductor wafer joined with other semiconductor memory chips. At this stage in the manufacture of semiconductor memory chips, extra circuits can be substituted when a faulty area in the primary memory array of memory elements is discovered. To date, many manufacturers in the United States and several Japanese manufacturers have reported circuits to implement the substitution of memory elements in a memory array necessary to accomplish repairs of faulty memory elements. The repaired semiconductor memory chips may thus pass all the electrical tests and be shipped or sold as semiconductor memory chips. Western Electric has recorded a factor of 30 percent improvement in yield in the early stages of semiconductor memory chip production thereby establishing the need and value of redundancy.
A publication by J. G. Posa, entitled "What To Do When The Bits Go Out", published in Electronics, July 28, 1981, pages 117-120, describes efforts by numerous companies to increase the yield of memory chips by incorporating some sort of redundancy at the wafer stage. At page 119 starting at the middle of the left-hand column, the substitution of spare bits, such as spare rows or columns, are discussed to replace faulty bits. Methods used by industry to substitute redundant memory bits include electrical fusing, wherein the fuses may be polysilicon or metal, laser cuts, or nonvolatile storage elements like floating gates. At the lower left-hand column of page 119 he suggests that the future use of nonvolatile elements to store bad addresses may be used in electrically erasable PROMs and perhaps even RAMs.
Specific redundancy circuits or memories using polysilicon fuses are described in a publication entitled "Designing Static RAMs For Yield As Well As Speed", by R. Sud and K. C. Hardee, appearing in Electronics, July 28, 1981, pages 121-126. FIG. 2b shows a latch including a fuse which may be blown to force the latch in a second state at all times. FIG. 3 shows spare decoders for addressing a spare column which may be switched in place of a faulty column of memory bits in a memory array. The replacement of a defective row in a memory array is also discussed.
Additional redundancy circuits utilizing polysilicon fuses are described in a publication entitled "Equipping A Line of Memories With Spare Cells", by R. Abbott, K. Kokkonen, R. I. Kung, and R. J. Smith, appearing in Electronics, July 28, 1981, pages 127-130. FIG. 1a shows a fuse in a circuit for either providing the true or complement address signal at its output. FIG. 2a shows circuitry for addressing a spare row and for disabling all other rows when the spare row is addressed. The electrical fuses are programmed following the step of testing the memory array and detecting the addresses of faulty bits. The fuses store the bad addresses of faulty bits and provides a signal to enable a spare row to be addressed at times the faulty bit is addressed while disabling the decoder to the row containing the faulty bit.
The use of polysilicon links opened up by a laser to achieve redundancy in memories is described in an article entitled "Using A Laser Beam To Substitute Good Cells For Bad", by R. T. Smith, appearing in Electronics, July 28, 1981, pages 131-134. FIG. 2a shows a decoder circuit having a laser programmable link for severing a bad row from its driver. FIG. 2b shows a spare decoder which may be programmed to respond to a specific address which would then be coupled to a spare row in the memory array. The laser programmable link measures approximately 3.times.14 micrometers and the laser spot size ranges from 7 to 8 micrometers. Prior to opening up links with a laser, a test program must be run locating the faulty bits. The laser is used to open up links in the memory circuits while the circuits are still on the wafer prior to dicing and packaging.
It is therefore desirable to provide a decoder which may be programmed electrically either at the wafer stage or after packaging.
It is further desirable to provide a programmable decoder that uses variable threshold transistors.
It is further desirable to provide a plurality of programmable decoders which may be programmed one at a time to allow the substitution of a spare row or spare column in place of a faulty row or faulty column of memory bits in a memory array.
It is further desirable to provide means for disabling the access of faulty rows or faulty columns when a spare row or spare column is substituted.
It is further desirable to provide a sequencer which includes variable threshold transistors to permit sequential programming of a plurality of decoders over extended periods of time, years, and with intervals of power supply voltage interruptions or loss.
It is further desirable to provide circuitry for disabling the redundant circuitry to permit inspection of the original memory array through the original row and column decoders of the memory array.